|
|
|
SPI 2009 Archives
Session 1: Packaging and Power Integrity Session chair: V. Ricchiuti, TechnoLabs R&D (I)
| | Fast Analysis of Power Distribution Networks using Waveform Relaxation | |
| Ram Achar, Michel Nakhla, Arvind Sridhar, Harjot Dhindsa, Douglas Paul | |
| Characterization and modeling of the power delivery networks of memory chips | |
| I.S. Stievano, I.A. Maio, L. Rigazio, F.G. Canavero, R.Izzi, A.Girardi, T. Cunha, H. Teixeira, J.C. Pedro | |
Session 2: Transmission Lines and High-Speed Channels Session chair: R. Khazaka, Univ. McGill (CAN)
| | Experimental Validation of the RC-Interconnect Effect Equalization with Negative Group Delay Active Circuit in
Planar Hybrid Technology | |
| Blaise Ravelo, André Pérennec and Marc Le Roy | |
| Multi-Gigabit Serial Link Emissions and Mobile Terminal Antenna Interference | |
| Martti Voutilainen, Markku Rouvala, Pia Kotiranta, Tapani von Rauner | |
| Compromised Impedance Match Design for Signal Integrity of Pogo Pins Structures with Different Signal-Ground
Patterns | |
| Ruey-Bo Sun, Ruey-Beei Wu, and Shih-Wei Haiso
| |
Session 3: 3D Modeling Session chair: F. G. Canavero, Politecnico di Torino, Dipartimento di Elettronica, Torino (I)
| | An Equivalent Circuit Model for the Identification of the Stub Resonance due to Differential Vias on PCB | |
| Vittorio Ricchiuti, Francesco de Paulis, Antonio Orlandi | |
| High Frequency Characterization and Modeling of High Density TSV in 3D Integrated Circuits | |
| C. Bermond, L. Cadix, A. Farcy, T. Lacrevaz, B. Fléchet, P. Leduc | |
| Investigation of the Interactions Between Vias and the Power-Bus | |
| Gerd Heinrich, Stefan Dickmann
| |
Session 7: Signal and Power Integrity Session chair: M. S. Nakhla, Carleton University, Department of Electronics, Ottawa (CAN)
| | Differential to Common Mode Conversion Due to Asymmetric Ground Via Configurations | |
| Renato Rimolo-Donadio, Xiaomin Duan, Heinz-Dietrich Brüns, Christian Schuster | |
| Supply Voltage Drop Study Considering On-Chip Self Inductance of a 32-bit Processor’s Power Grid | |
| Daniel A. Andersson, Björn Nilsson, Johnny Pihl, Lars Svensson, and Per Larsson-Edefors | |
| Extraction of Broadband Error Boxes for Microprobes and Recessed Probe Launches for Measurement of Printed
Circuit Board Structures | |
| Miroslav Kotzev, Renato Rimolo-Donadio, Christian Schuster | |
| Identification of Interconnect Failure Mechanisms Using RF Impedance Analysis | |
| Daeil Kwon, Michael H. Azarian, and Michael Pecht | |
|
Poster Session Session chair: Y. Quéré, Brest University, Lab-STICC (F)
| | Modeling the Interconnection of a Pseudo-Differential Link Using a Wide Return Conductor | |
| Frederic Broydé, Evelyne Clavelier | |
| Sensitivity of output response to geometrical dimensions in VLSI interconnects | |
| Agnieszka Ligocka-Wardziñska, Wojciech Bandurski | |
| Low-Impedance and High-Q Transmission Line for mmw VCO | |
| You Nomiyama, Win Chaivipas, Kenichi Okada, and Akira Matsuzawa | |
| BER Simulation for High-Speed Serial Links with Crosstalk, Noise, ISI and Jitter using Quasi-Analytical Method | |
| Dingqing Lu, Chunxing Huang, Xiaoqing Dong and Daoxue Hu | |
| Integral Power Net Integrity Analysis of a packaged u-Controller System including the u-Controller on-Chip Power Net Distribution | |
| Ekkehard Miersch, Mehmet Goekcen , Thomas Steinecke | |
| Effect of Underlayer Dummy Fills on On-Chip Transmission Line | |
| Akira Tsuchiya and Hidetoshi Onodera | |
| Towards Supply-Grid-Based Derating of Timing Margins | |
| Svensson, Pihl, Andersson, Nilsson, Larsson-Edefors | |
| Analysis of EMI Dependence on Signal Duty and Supplied Voltage | |
| Pilsoo Lee, Jae-Kyung Wee, Inchae Song, and Boo-Gyoun Kim | |
| Measurement and simulation correlation of backplane serdes channel | |
| Perry Qu | |
|
|
|
|
|